KSZ8863MLL/FLL/RLL contains two 10/100 physical layer transceivers and three MAC units with an integrated layer 2 managed switch. KSZ8863MLL/FLL/RLL has the flexibility to reside in either a managed or unmanaged design. In a managed design, the host processor has complete control of KSZ8863MLL/FLL/RLL via the SMI interface, MIIM interface, SPI bus, or I2C bus. An unmanaged design is achieved through I/O strapping and/or EEPROM programming at system reset time. On the media side, KSZ8863MLL/FLL/RLL supports IEEE 802.3 10BASE-T and 100BASE-TX on both PHY ports. Physical signal transmission and reception are enhanced through the use of patented analog circuitries that make the design more efficient and allow for lower power consumption and smaller chip die size.
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